CB-ACC-36【PDF 49/58 页】ANTENNA 1/2WV 2.4GHZ 10CM RPSMA

Version 1.17 2011-09

A.2 Design Examples

This section contains design examples for all interfaces on J2, J3, J6, J7 and J8. The con-

nector type that suits a specific application depends on the needed signal and the preferred

interface type (wires, flexfilm, board-to-board or SMD).

A.2.1 Logic Levels

A 3.0/3.3V host system can be connected directly to the logic level pins (BLUE, UART-TxD /

UART-RxD etc). A serial 100& resistor shall be used (see Figure 11) for protection, see Ta-

ble 12 for logic levels characteristics.

A 5V host system can easily be adjusted to the logic levels. A host system output signal can

use a resistive divider (1.8k&/2.2k&) to adjust the levels. This is applicable for speeds up to

115.2kBits/s. The divider can be improved by adding a logic buffer (74HCT08) for higher

speeds (see Figure 12). The host system input pins could require a buffer (see Figure 12)

depending on the logic level requirements (see Table 12).

The 74HCT08 gate is also available in a single gate package (74AHCT1G08).

Figure 11: Logic levels interface to a 3/3.3V

system. A protective 100&

& &

& resistor is used.

Figure 12: Interface example with logic levels to a 5V

system.

A 5V system with open collector outputs is designed in Figure 13.

Figure 13: Open collector outputs.

发布紧急采购，3分钟左右您将得到回复。

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购